1. Field of the Invention
This invention relates to a pulse discriminating system for reply signals and the like in transponders, and more particularly to a pulse discriminating system for reply signals and the like which can independently and correctly discriminate between respective pulse trains in the case where a plurality of reply signals overlap each other with respect to time in onboard transponders in aircraft.
2. Description of the Prior Art
In general, for air traffic control, principal aircraft are equipped with transponders and when a interrogation signal transmitted by a ground control system and the like is received by such aircraft, they send back prescribed information such as its identity, altitude and the like.
In a particular case, similar information is also exchanged between aircraft. One example of a signal handled in such a transponder as described above is as illustrated in FIG. 3 which shows an example of a transponder reply signal in the so-called mode C wherein 15 pulses at maximum, each having a width of 0.45 .mu.s, are arranged with a spacing of 1.45 .mu.s.
Among them, the first and least pulses F.sub.1 and F.sub.2 are referred to as bracket pulses (BKT) and are fixed. An interval between these BKT pulses F.sub.1 and F.sub.2 is 20.3 .mu.s, and 13 pulses C.sub.1, A.sub.1, A.sub.2, . . . , D.sub.4 are arranged between the former pulses as shown in FIG. 3. Logic "1" or "0" is assigned in response to the presence of pulses at the respective positions to encode advanced information and the like so as to display them.
In decoding an information signal which has been encoded by means of such a pulse train, it is necessary for the presence of a pulse at the respective positions to be detected. In this connection, heretofore, a pulse discriminating circuit to be used for the above case has generally been constructed from a 20.3 .mu.s delay circuit DL.sub.1 and a required number of AND circuits (AND gates) as shown in FIG. 2.
More specifically, two signals, one of which is the reply signal itself and the other is a reply signal which has been delayed by 20.3 .mu.s by causing the former to pass through said delay circuit DL.sub.1 are inputted to an AND circuit (AND gate) Q.sub.a to obtain BKT as its AND output and, at the same time, to input each output obtained from thirteen taps provided in said delay circuit DL.sub.1 and delayed by 1.45 .mu.s in a tap into one input terminal of each of a total of thirteen AND gates Q.sub.b to Q.sub.n, respectively, whilst BKT (bracket pulses) outputted from said AND gate Q.sub.a is inputted to each of the other input terminals of each of said thirteen gates, whereby discriminated thirteen information pulses are output at the outputs of these AND gates Q.sub.b to Q.sub.n.
In order to facilitate understanding of the present invention, operation in the above-mentioned circuit construction shown in FIG. 2 will be described in detail hereinbelow by referring to the timing chart shown in FIG. 4.
The timing chart consisting of FIGS. 4(a) through (g) indicates the timing relationship of the input and output of the delay circuit DL.sub.1 in FIG. 2 as well as pulses output at the respective taps wherein (a) designates the input reply signal, (b) through (f) designate the thirteen tap outputs derived therefrom with each 1.45 .mu.s delay interval, and (g) designates the output signal at the output of said delay circuit DL.sub.1, respectively.
First, since AND of pulse trains indicated by FIGS. 4(a) and (g) is obtained in the first AND gate Q.sub.a, a pulse output having 0.45 .mu.s width, i.e., a BKT pulse is output as the AND of both the last pulse at (a), i.e., F.sub.2 and the first pulse delayed by 20.3 .mu.s at (g), i.e., F.sub.1. F.sub.1 and F.sub.2 are positively present as bracket pulse as mentioned above, so that the output "1" is inevitably obtained at the output of said AND gate Q.sub.a.
Next, the BKT pulse is inputted to each of the other thirteen inputs of the second AND gate Q.sub.b to the fourteenth AND gate Q.sub.n. For example, these AND gates function such that the AND gate Q.sub.b outputs an AND output derived from said BKT pulse and the second pulse shown in FIG. 4(b), i.e., the C.sub.1 pulse, further the AND gate Q.sub.c outputs AND of the BKT pulse and the third pulse indicated in FIG. 4(c), i.e., the A.sub.1 pulse, and the AND gate Q.sub.d outputs AND derived from the fourth pulse indicated in FIG. 4(d), i.e., the C.sub.2 pulse. Thus, the AND output of such pulses which have been successively delayed as described above and the BKT pulse form a pulse train delivered successively every 1.45 .mu.s time interval in a time serial manner is obtained as a parallel pulse signal after a delaying time interval of 20.3 .mu.s. As a result, "1" is obtained if a pulse exists in respective pulse positions and if not, "0" is obtained at the respective AND gates so that information delivered from a transmitter can be discriminated and reproduced.
In such conventional pulse discriminating method as mentioned above, however, when a plurality of reply signals are garbled, they cannot be discriminated, and there is a fear of erroneous decoding.
Namely, if the case where two reply signals #1 and #2 with only a small time difference therebetween is taken as an example as shown in FIG. 5, these two signal pulses are received as the sum of both pulses as indicated in FIG. 5 #1and #2.
Hence, there is a problem that when the signal as described above is decoded by the use of said conventional discriminating circuit, an AND signal based on #1and #2 signals is output, but such AND signal is quite different from that derived from said #1 and #2 pulse trains so that this becomes a cause of an erroneous decoding.
Accordingly, the present invention has been made to eliminate the problems involved in the pulse discriminating system for reply signals and the like in the conventional transponders as described above, and an object of the present invention is to provide a pulse discriminating system for reply signals and the like in transponders.